/*

Copyright (c) 2015-2016 Alex Forencich

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.

*/

// Language: Verilog 2001
/*-----------------------------------------------------------------------------------------------*\
wb_iic #
(
    .DATA_WIDTH(32),                  // width of data bus in bits (8, 16, 32, or 64)
    .ADDR_WIDTH(32)                  // width of address bus in bits
) u_wb_iic (
    .clk( clk),
    .rst( rst),

    .wbm_adr_i( ),    // ADR_I() address
    .wbm_dat_i( ),    // DAT_I() data in
    .wbm_dat_o( ),    // DAT_O() data out
    .wbm_we_i ( ),    // WE_I write enable input
    .wbm_sel_i( ),    // SEL_I() select input
    .wbm_stb_i( ),    // STB_I strobe input
    .wbm_ack_o( ),     // ACK_O acknowledge output

    .scl0  ( ),
    .sda0  ( )
);
\*-----------------------------------------------------------------------------------------------*/
`timescale 1ns / 1ps
`ifndef  __WB_IIC__
`define  __WB_IIC__
/*
 * Wishbone register
 */
module wb_iic #
(
    parameter DATA_WIDTH = 32,                  // width of data bus in bits (8, 16, 32, or 64)
    parameter ADDR_WIDTH = 32,                  // width of address bus in bits
    parameter SELECT_WIDTH = (DATA_WIDTH/8)     // width of word select bus (1, 2, 4, or 8)
)
(
    input  wire                    clk,
    input  wire                    rst,

    // master side
    input  wire [ADDR_WIDTH-1:0]   wbm_adr_i,   // ADR_I() address
    input  wire [DATA_WIDTH-1:0]   wbm_dat_i,   // DAT_I() data in
    output reg  [DATA_WIDTH-1:0]   wbm_dat_o,   // DAT_O() data out
    input  wire                    wbm_we_i,    // WE_I write enable input
    input  wire [SELECT_WIDTH-1:0] wbm_sel_i,   // SEL_I() select input
    input  wire                    wbm_stb_i,   // STB_I strobe input
    output reg                     wbm_ack_o,   // ACK_O acknowledge output
    // iic0 的io 
    output reg    scl0 , 
    inout  wire   sda0 

);

reg sda0_r ;
assign sda0 = (sda0_r) ? 1'bz : 1'b0 ;

always @(posedge clk ) begin
    if(rst) begin
        wbm_ack_o <= 1'b0 ;
        wbm_dat_o <= 32'h0 ;
        sda0_r <= 1'b1 ;
    end else begin 
        wbm_ack_o <= 1'b0 ;
        //写数据 
        if(wbm_stb_i & wbm_we_i & !wbm_ack_o) begin
            wbm_ack_o <= 1'b1 ; 
            
            case (wbm_adr_i) 
                32'h0000_0000 : begin
                    {sda0_r , scl0 } <= wbm_dat_i[1:0] ;
                    $display("%d ns  | Write @ 0x%08x: sda0,scl0=%02b [iic0]",$time  , wbm_adr_i ,wbm_dat_i[1:0] ) ;
                end
            endcase 
        end

        // 读数据 
        if(wbm_stb_i & !wbm_we_i & !wbm_ack_o) begin
            wbm_ack_o <= 1'b1 ; 
            case (wbm_adr_i) 
                32'h0000_0000, 32'h0000_0004 : begin
                    wbm_dat_o[0] <= scl0 ;
                    wbm_dat_o[1] <= sda0 ;
                    $display("%d ns  | Read  @ 0x%08x: sda0,scl0=%02b [iic0]",$time  , wbm_adr_i ,{sda0,scl0} ) ;
                end
            endcase 
        end 
    end 
end

endmodule


`endif  